1. Field of the Invention
The present invention generally relates to a semiconductor device and a method of controlling the same.
Priority is claimed on Japanese Patent Application No. 2011-069078, filed Mar. 28, 2011, the content of which is incorporated herein by reference.
2. Description of the Related Art
Synchronized semiconductor devices exist which operate in synchronization with an externally supplied clock signal, capture a command to activate or deactivate an internal circuit in synchronization with the clock signal, and control the operation and stopping of the internal circuit.
Japanese Patent Application Publication No. JPA 11 (1999)-144497 and Japanese Patent Application Publication No. JPA 2001-126480 disclose the followings. In the case of testing the performance of a synchronized semiconductor device, a clock signal and a command are supplied from a semiconductor device testing system (tester). In performance testing of a synchronized semiconductor device, in the case in which the period of time (tRP time) from the capture by the semiconductor device of a clock signal and pre-charge command (command that deactivates the internal circuit) until the capture of a clock signal and an activate command (command that activates the internal circuit) is made short, there is a performance limit test called a tRP test that test whether or not the semiconductor device can operate (refer to Patent Reference 1 and Patent Reference 2).
In the synchronized semiconductor device described in Patent Reference 1, the timing of generating a pre-charge signal output by a pre-charge circuit that deactivates the internal circuit is delayed by a prescribed time by a test mode signal and a delay circuit. The synchronized semiconductor device has a test circuit that, by delaying the timing of generating the pre-charge signal, delays the timing of deactivating the internal circuit and sets the tRP time to be short (refer to FIG. 22 and FIG. 23 in Japanese Patent Application Publication No. JPA 11 (1999)-144497.